1. Field of the Invention
The disclosed subject matter relates generally to the field of semiconductor device manufacturing, and more particularly, to a multi-layer barrier layer stack for an interconnect structure.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed in and above the surface of a semi-conductive substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnect structures. The back end of line (BEOL) is the second portion of integrated circuit fabrication where the individual devices (transistors, capacitors, resistors, etc.) get interconnected with wiring elements. BEOL generally begins when the first layer of metal is deposited on the wafer. It includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed in and above the substrate. Thus, these conductive interconnect structures must be made in multiple layers to conserve plot space on the semiconductor substrate.
The conductive interconnect structures are typically accomplished through the formation of a plurality of conductive lines and conductive plugs, commonly referred to as contacts or vias, formed in alternating layers of dielectric materials formed on the device. As is readily apparent to those skilled in the art, the conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. The conductive lines that connect the various interconnect structures are commonly formed in trenches defined in the dielectric layers.
A contact is generally used to define an interconnect structure (e.g., using polysilicon or metal) to an underlying polysilicon layer (e.g., source/drain or gate region of a transistor), while a via denotes a metal to metal interconnect structure. In either case, a contact opening or via opening is formed in an insulating layer overlaying the conductive member. A second conductive layer is then formed over the contact or via opening and electrical communication is established with the conductive member.
One technique for reducing the size of the features formed on the semiconductor device involves the use of copper for the lines and interconnections in conjunction with new dielectric materials having lower dielectric constants than previously achievable with common dielectric material choices. Standard dielectric materials such as silicon dioxide, TEOS, and F-TEOS have dielectric constants greater than 3. The new dielectric materials, commonly referred to as low-k dielectrics, have dielectric constants less than 3, and thus, allow greater device densities, due to their more efficient isolation capabilities. One such low-k dielectric is sold under the name of Black Diamond, by Applied Materials, Inc.
Typical interconnect features include a metal stack that is made up of three basic elements: a barrier layer, a seed layer, and bulk fill. The barrier layer serves to inhibit migration or diffusion of copper into the dielectric and also to inhibit oxygen diffusion from the dielectric into the interconnect feature. The seed layer provides a favorable surface to nucleate islets for copper grain growth, improves wettability of copper over the topography to minimize agglomeration, protects the barrier material from attack in the copper plating bath, and provides a dopant material for diffusion into the copper to mitigate electromigration (EM) and stress migration (SM).
In a narrow BEOL pitch, the barrier and seed layers must be relatively thin to accommodate the geometry while leaving enough room for the bulk copper fill. Due to continuous scaling to smaller dimensions, it becomes more difficult to create barrier and seed layers that are capable of performing their functions.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.